Xilinx Zynq UltraScale+ MPSoC AI 100G Optical fiber HPC FPGA Core Board XCZU19EG


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  • Ean

  • Price

    $ 7925


Xilinx Zynq UltraScale + MPSoC FPGA + AI High-end FPGA Board

Support XILINX Vitis-AI DPU; 100 Gb/s optical fiber

High speed optical fiber network communication, high-speed data exchange and storage, industrial control, deep learning, AI intelligence, cloud computing, 4K video transmission and processing

  • ·ARM CPU

    4x ARM CORTEX-A53 + 2x ARM CORTEX-R5

  • ·GPU

    Mali™-400 MP2 GPU

  • ·8GB DDR4

    PS 8GB DDR4, Expansion port is reserved at the PL end, which can expand 32GB DDR4

  • ·FLASH Storage


  • ·100 Gb/s Optical fiber

    4x 100G optical fiber interface

  • ·FMC HPC

    2x FMC HPC



Development software version: vitis2020.1, Linux version: petalinux5.4.0-xilinx-v2020.1 all supporting materials of the development board are provided through Baidu online disk. After purchase, please contact customer service to obtain

Development Environment
01. Vitis Installation
02. Install Virtual Machine and Ubuntu System
03. Install Linux Version of Vitis Software on Ubuntu
04. Petalinux tool Installation

05. NFS Service Software Installation
06. QT Creator Development Environment
07. Linux Common Commands
Remark:Vitis 2020.1

FPGA Experiment Tutorial  
01. Introduction to Ultrascale+ MPSoC
02. PL's "Hello World" LED Experiment
03. PL Side DDR4 Read and Write Test Experiment
04. Bit error rate test of gty transceiver ibert experiment
05. Experience ARM, bare metal output "Hello World"
06. PS RTC Interrupt Experiment
07. PS Side Use of EMIO
08. PS Side UART Read and Write Control
09. PS Side Use of CAN
10. PS Side Use of I2C
11. PS Side Use of Display Port
12. PS Side SD Card Read and Write
13. PS Side Use of Ethernet (LWIP)

14. PS Side Remote Update QSPI Flash by Ethernet
15. Use of System Monitor
16. PS Side Use of EMIO
17. PL Side Use of AXI GPIO
18. PL Side RS485 Test
19. PL Side Use of Ethernet
20. Custom IP experiment
21. Use of Dual Core AMP
22. Use of“Free RTOS”under ZYNQ
23. PL Read and Write PS DDR Data
24. Realize PS and PL Data Interaction through BRAM
25. DP Acquisition and Display Based on AN5641 Module

HLS Experiment Tutorial
01. Getting to Know Vitis HLS
02. Vitis HLS Getting Started
03. HLS Interacts with CPU Registers
04. How to use the built-in Functions in the xfopencv Library
05. Image RGB to Grayscale Conversion
06. Image RGB to YCrCb
07. Image Morphological Filtering

08. Image overlay
09. Image Contrast Adjustment
10. Corner Detection
11. SOBEL operator realizes edge detection
12. Canny Operator Realizes Edge Detection
13. How to Implement opencv Simulation With Vitis HLS

Linux Basic Tutorial
01. Customizing Linux with Petalinux
02. Program hello world
03. Gpio Control LED
04. Add Boot Scripts and User Files
05. SD Card Root File System
06. QT and OPENCV Cross-Compilation 3nvironment

07. Use Vitis to Develop Linux Programs
08. Vitis Accelerates Basic Platform Creation
09. NVMe SSD operation under Linux
10. From QSPI Flashstart-up Linux
11. Starting Linux from EMMC
Remark: Linux Version petalinux 5.4.0-xilinx-v2020.1

Linux Driver Tutorial
01. Character Device
02. A New Way of Writing Character Devices
03. Device Tree and of Function
04. pinctrl and gpio Subsystem
05. Concurrent Processing
06. Pio input
07. Timer
08. Interrupt
09. Blocking IO
10. Non-Blocking IO
11. Asynchronous IO
12. Platform
13. Platform and Device Tree

14. MISC device driver
15. Input Subsystem
16. PWM Drive
17. I2C Driver
18. USB Driver
19. SPI Drive
20. Uart Driver
21. Block Device Driver
22. NIC driver
23. DMA Driver
24. Multi-touch screen driver
25. LCD Drive

Linux Application Development Tutorial                
01. Building a Minimalist Working Environment
02. Hello World with Remote Debugging
03. OpenCV Edge Detection
04. OpenCV+Qt Face Detection

05. GStreamer's Camera Display
06. Qt+DRM+Gstreamer Camera Display
07. Qt+GPU Camera Display
08. Linux Register Operation

Vitis-AI Basic
01. Docker Environment Construction
02. Vitis-AI Development Process

03. Neural Network Training based on Keras Framework
04. Debugging Tools


·Core Board SOM



Core Board Main Parameters



Chip CPU

4x ARM Cortex-A53, 1.333GHz; Dual Core Cortex™-R5, 533MHz

Chip GPU

Mali™-400 MP2

Chip level

Speed grade -2, industrial grade, working temperature -40°c~85°C

PS-end High Speed Connection

PCIe Gen2 x4, 2x USB3.0, SATA 3.1, DisplayPort, 4x Tri-mode Gigabit Ethernet

PS-end General Connection

2x USB 2.0, 2x SD/SDIO, 2 x UART, 2 x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO

Logic Cells


CLB Flip-Flops


Look Up Tables (LUTs)


Global Clock


PCIE Gen 3x16


100G Ethernet


PL GTY 32.75Gb/s


Max. Distribu- ted RAM


Total Block RAM




DSP Slices


150G Interlaken


PL GTH 16.3Gb/s


Interface And Function


PS DDR4, 4 Pieces of 1G DDR4, 4GB Total, 64bit, Data Speed 2400Mbps
PL has a 260 pin DDR4 sodimm socket (self purchased memory module is required)

QSPI Flash

Two pieces of 512Mbit QSPI flash, a total of 1024mbit, are used for the storage of zboot files, system files and user data of zynq chip

eMMC Flash

32GB eMMC FLASH memory chip, users store operating system files or other user data

PCIe x8 Slot

PCIe x8 slot 1-way PCIe x8 slot is used for PCIe x8 communication, connecting PCIe x8, x4, x2, x1 PCIe boards to realize PCIe data communication. It supports PCI Express 2.0 standard, and the single channel communication rate can be as high as 5gbaud.

DP Interface

Mini Display Port up to 4K@30Hz or 1080P@60Hz Output ( ALINX customized DP to HDMI cable, need to buy Separately )

100G Optical fiber interface

Four QSFP28 optical fiber interfaces provide independent transmission and reception channels, Data rate is 100Gbps


Two FMC HPC expansion ports, external Xilinx or ALINX FMC daughter boards ( HDMI input and output module, binocular camera module, high-speed AD module, etc )

CAN Bus Interface x2

Used for CAN Communication Service

RS485 Bus Interface x2

Used for 485 communication Service

MIPI Interface

1 channel Mipi camera input interface, used to connect Mipi camera module

M.2 NVME Interface

Used to Connect the M.2 SSD Solid State Drive ( Need to Buy it Yourself )

USB to serial port

PS and PL have one UART to USB interface respectively. Used for debugging communication with computer
The third UART port is led out from the PS end through a 1mm spacing, 10-PIN FPC connector, which can be connected to peripheral devices such as serial port screen

Ethernet interface

One Gigabit Ethernet interface at PL and PS ends respectively to exchange Ethernet data with computers or other network devices

USB 3.0 x4

Used to Connect External USB Peripherals

SMA Interface

3 pairs of differential SMA interfaces are used for external high-speed input and output signals

SATA Interface

4-way SATA interface for connecting peripherals such as hard disks


10-pin 2.54mm standard JTAG port for downloading and debugging of field programmers

Clock Configuration

A passive crystal provides 32.768 KHz real-time clock source for PS system
A crystal oscillator provides 33.333MHz clock input for the PS section
A differential 200MHz PL system clock source for DDR4 controller reference clock

Real Time Clock

1 built-in RTC real-time clock


EEPROM 24LC04 with 1 piece of IIC interface

Temperature Sensor

Sensor Chip LM75, Used to Detect the Ambient Temperature

SD Card Slot

1 Micro SD Card Slot, Support SD Mode and SPI Mode


1 power indicator, 1 DONE configuration indicator, 2 user indicators


3 KEYs, 1 Reset KEY, 2 User KEYs

Power Supply Parameters

Voltage Input

+12V DC

Current Input

Max. Current 3A

Package List

FPGA Board


DC Fan (Fixed on the Board)


Mini USB Cable


USB Downloader Cable

1 Set

12V Power Adapter


Transparent Protection Board


TF Card


Card Reader


Structure Size

Size Dimension

250mm x 170mm

Number of Layers

Adopt 8-layer PCB design, and reserve independent power supply layer and GND layer



AI recognition detection, depth computing learning

Intelligent identification and detection, image and video processing, security monitoring, machine vision, fire monitoring,  
traffic safety, smart construction site, smart hotel, smart agriculture, Internet of Things

Vehicle Identification

Infrared Vehicle Identification


Pedestrian recognition

Indoor Person Recognition

Fire detection

Helmet detection

Concrete defect detection

PCB defect detection

Rich extension interface

Multi domain development and high-speed transmission

Intelligent Recognition, Image and Video Processing Security Monitoring, Machine Vision


Rich peripheral interfaces: 2x FMC HPC interfaces, 4x M.2 SSD interfaces, 1x PCIe main mode slot, 4x SATA interfaces, 3x SMA interfaces,1x DP interface, 4x 100G optical fiber interfaces, 4x USB3.0 interfaces, 2x Gigabit Ethernet interfaces, 3x UART interfaces, 1x TF card slot, 2x CAN bus interfaces, 2x RS485 interfaces, and 1 x Mipi camera interface

It supports AI intelligence, cloud computing, high-speed optical fiber network communication, high-speed data storage, video image processing, pre project verification, machine vision, industrial control and other applications

QSFP28 Optical Fiber Interface

100G Optical fiber transmission communication

Data rate of 100Gbps




Intelligent Identification, Medical Security Vehicle Digital, Industrial Control, Smart Grid

Video Image Collection Demo Camera Acquisition System

MIPI Camera Module AN5641 On-Board Demo

     The MIP Camera Module AN5641 for Video Capture and Displays it on the Monitor through the Mini DP Interface

The warranty period of all products sold is 12 months, of which FPGA chips and LCD screens are wearing parts and are not covered by the warranty. All accessories and gifts are not covered under warranty.

Alinx Electronic Limited 沪ICP备13046728号